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M39P0R9080E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 256 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package
Feature summary
Multi-Chip Package - 1 die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash memory - 1 die of 256 Mbit (4 Banks of 4Mb x16) Low Power Synchronous Dynamic RAM Supply voltage - VDDF = VCCP = VDDQ = 1.7 to 1.95V - VPPF = 9V for fast program Electronic signature - Manufacturer Code: 20h - Device Code: 8819 ECOPACK(R) package available
FBGA
TFBGA105 (ZAD) 9 x 11mm

100,000 program/erase cycles per block Block locking - All Blocks locked at power-up - Any combination of Blocks can be locked with zero latency - WPF for Block Lock-Down - Absolute Write Protection with VPPF = VSS Common Flash Interface (CFI)
Flash memory
Synchronous / asynchronous read - Synchronous Burst Read mode:
108MHz, 66MHz
LPSDRAM
- Asynchronous Page Read mode - Random Access: 96ns
Programming time - 4.2s typical Word program time using Buffer Enhanced Factory Program command Memory organization - Multiple Bank Memory Array: 64 Mbit Banks - Four Extended Flash Array (EFA) Blocks of 64 Kbits Dual operations - program/erase in one Bank while read in others - No delay between read and write operations Security - 64-bit unique device number - 2112-bit user programmable OTP Cells
256 Mbit synchronous dynamic RAM - Organized as 4 Banks of 4 MWords, each 16 bits wide Synchronous burst read and write - Fixed Burst Lengths: 1, 2, 4, 8 words or Full Page - Burst Types: Sequential and Interleaved. - Clock Frequency: 133 MHz (7.5ns speed class) - Clock Valid to Output Delay (CAS Latency): 3 at 133 MHz Automatic and controlled precharge Low-power features: - Partial Array Self Refresh (PASR), - Automatic Temperature Compensated Self Refresh (TCSR) - Driver Strength (DS) - Deep Power-Down Mode Auto Refresh and Self Refresh

November 2007
Rev 2
1/23
www.numonyx.com 1
Contents
M39P0R9080E0
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 10 Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory Chip Enable input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Write Protect input (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Deep Power-Down (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Chip Select (ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Column Address Strobe (CASS) . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Row Address Strobe (RASS) . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Write Enable (WS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Clock input (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Clock Enable (KES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LPSDRAM lower/upper data input/output mask (LDQMS/UDQMS) . . . . . 13 Flash memory VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LPSDRAM VDDS supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash memory VPPF Program supply voltage . . . . . . . . . . . . . . . . . . . . . . 13 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/23
M39P0R9080E0
Contents
5 6 7 8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
List of tables
M39P0R9080E0
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 7. Table 8. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/23
M39P0R9080E0
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 20
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Summary description
M39P0R9080E0
1
Summary description
The M39P0R9080E0 combines two memory devices in one Multi-Chip Package:

512-Mbit Multiple Bank Flash memory (the M58PR512J) 256-Mbit Low Power Synchronous DRAM (the M65KA256AF)
The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58PR512J and M65KA256AF datasheets, where all specifications required to operate the Flash memory and SDRAM components are fully detailed. These datasheets are available from the Numonyx website www.numonyx.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is delivered in a Stacked TFBGA105 package. In order to meet environmental requirements, Numonyx offers the M39P0R9080E0 in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. The M39P0R9080E0 is supplied with all the bits erased (set to `1').
6/23
M39P0R9080E0 Figure 1. Logic diagram
VDDF VDDQ 25 A0-A24 BA0-BA1 EF GF WF RPF WPF LF KF DPDF ES WS KES KS RASS CASS UDQMS LDQMS VSS M39P0R9080E0 WAITF 2 VDDS VPPF 16
Summary description
DQ0-DQ15
Ai12095
7/23
Summary description Table 1.
A0-A24
(1)
M39P0R9080E0 Signal names
Address Inputs Common Data Input/Output Common Flash and LPSDRAM Power Supply for I/O Buffers Flash Memory Optional Supply Voltage for Fast Program & Erase Flash Memory Power Supply LPSDRAM Power Supply Ground Not Connected Internally Do Not Use as Internally Connected
DQ0-DQ15 VDDQ VPPF VDDF
VDDS
VSS NC DU Flash Memory EF GF WF RPF WPF LF KF WAITF DPDF Low Power SDRAM ES WS KS KES CASS RASS BA0, BA1 UDQMS LDQMS
Chip Enable input Output Enable Input Write Enable input Reset input Write Protect input Latch Enable input Burst Clock Wait Output Deep Power-Down
Chip Enable Input Write Enable input LPSDRAM Clock input LPSDRAM Clock Enable input Column Address Strobe Input Row Address Strobe Input Bank Select Inputs Upper Data Input/Output Mask Lower Data Input/Output Mask
1. A13-A24 are Address Inputs for the Flash memory component only.
8/23
M39P0R9080E0 Figure 2. TFBGA connections (top view through package)
1 2 3 4 5 6 7 8
Summary description
9
A
DU
A4
A6
A7
A19
A23
A24
NC
DU
B
A2
A3
A5
A17
A18
DPDF
A22
NC
A16
C
A1
VSS
VSS
VSS
VDDS
VSS
VSS
VSS
A15
D
A0
NC
VDDS
VDDF
LF
VDDF
VDDS
NC
A14
E
WPF
WF
NC
NC
NC
A21
A10
A13
F
NC
ES
CASS
RASS
NC
A20
A9
A12
G
NC
NC
EF
BA0
KES
RPF
A8
A11
H
NC
NC
NC
BA1
NC
WS
GF
UDQMS
LDQMS
J
VPPF
VDDQ
VDDQ
VDDF
KS
VDDF
VDDQ
VDDQ
WAITF
K
DQ2
VSS
VSS
VSS
KF
VSS
VSS
VSS
DQ13
L
DQ1
DQ3
DQ5
DQ6
DQ7
DQ9
DQ11
DQ12
DQ14
M
DU
DQ0
NC
DQ4
DQ8
DQ10
NC
DQ15
DU
AI10961
9/23
Signal descriptions
M39P0R9080E0
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device.
2.1
Address inputs (A0-A24)
A0-A12 are common to the Flash memory and LPSDRAM components. A13-A24 are Address Inputs for the Flash memory component only. In the Flash memory, the Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. In the LPSDRAM, the A0-A12 Address Inputs are used to select the row or column to be made active. If a column is selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High (set to `1') during Read or Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to `0') during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle.
2.2
LPSDRAM Bank Select Address Inputs (BA0-BA1)
The BA0 and BA1 Bank Select Address Inputs are used by the LPSDRAM to select the bank to be made active. The LPSDRAM must be enabled, the Row Address Strobe, RASS, must be Low, VIL, the Column Address Strobe, CASS, and WS must be High, VIH, when selecting the addresses. The address inputs are latched on the rising edge of the clock signal, KS.
2.3
Data Inputs/Outputs (DQ0-DQ15)
In the Flash memory, the Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. In the LPSDRAM, the Data Inputs/Outputs are common to all memory components. They output the data stored at the selected address during a Read operation, or are used to input the data during a write operation.
2.4
Flash memory Chip Enable input (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VIL and Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have EF and ES all at VIL at the same time, only one memory component should be enabled at a time.
10/23
M39P0R9080E0
Signal descriptions
2.5
Flash memory Output Enable (GF)
The Output Enable input controls data outputs during the Bus Read operation of the memory.
2.6
Flash memory Write Enable (WF)
The Write Enable input controls the Bus Write operation of the Flash memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.7
Flash memory Write Protect input (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See M58PR512J datasheet for details).
2.8
Flash memory Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58PRxxxJ datasheet for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to the M58PRxxxJ datasheet).
2.9
Flash memory Deep Power-Down (DPDF)
The Deep Power-Down input is used to put the Flash memory in Deep Power-Down mode. When the Flash memory is in Standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the Deep Power-Down input will cause the memory to enter the Deep Power-Down mode. When the device is in the Deep Power-Down mode, the memory cannot be modified and the data is protected. The polarity of the DPDF pin is determined by ECR14. The Deep Power-Down input is active Low by default.
11/23
Signal descriptions
M39P0R9080E0
2.10
Flash memory Latch Enable (LF)
The Latch Enable input latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.11
Flash memory Clock (KF)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations.
2.12
Flash memory Wait (WAITF)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in advance.
2.13
LPSDRAM Chip Select (ES)
The Chip Select input ES activates the LPSDRAM state machine, address buffers and decoders when driven Low, VIL. When ES is High, VIH, the device is not selected.
2.14
LPSDRAM Column Address Strobe (CASS)
The Column Address Strobe, CASS, is used in conjunction with Address Inputs A8-A0 and BA1-BA0, to select the starting column location prior to a Read or Write.
2.15
LPSDRAM Row Address Strobe (RASS)
The Row Address Strobe, RASS, is used in conjunction with Address Inputs A11-A0 and BA1-BA0, to select the starting address location prior to a Read or Write.
2.16
LPSDRAM Write Enable (WS)
The Write Enable input, WS, controls writing to the LPSDRAM.
2.17
LPSDRAM Clock input (KS)
The Clock signal, KS, is used to clock the Read and Write cycles. During normal operation, the Clock Enable pin, KES, is High, VIH. The clock signal KS can be suspended to switch the device to the Self Refresh, Power-Down or Deep Power-Down mode by driving KES Low, VIL.
12/23
M39P0R9080E0
Signal descriptions
2.18
LPSDRAM Clock Enable (KES)
The Clock Enable, KES, pin is used to control the synchronizing of the signals to Clock signal KS. The signals are clocked when KES is High, VIH When KES is Low, VIL, the signals are no longer clocked and data Read and Write cycles are extended. KES is also involved in switching the device to the Self Refresh, Power-Down and Deep Power-Down modes.
2.19
LPSDRAM lower/upper data input/output mask (LDQMS/UDQMS)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals used to mask the Read or Write data. The DQM latency is two clock cycles for read operations and there is no latency for write operations.
2.20
Flash memory VDDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supply for all operations (Read, Program and Erase).
2.21
LPSDRAM VDDS supply voltage
VDDS provides the power supply to the internal core of the LPSDRAM component. It is the main power supply for all operations (Read and Write).
2.22
VDDQ supply voltage
VDDQ is common to the Flash memory and LPSDRAM components. It provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDDF for the Flash memory, or VDDS for the LPSDRAM. VDDQ can be tied to VDDF or VDDS, or can use a separate supply.
2.23
Flash memory VPPF Program supply voltage
VPPF is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see the M58PRxxxJ datasheet for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.
13/23
Signal descriptions
M39P0R9080E0
2.24
VSS ground
VSS ground is common to the LPSDRAM and Flash memory components. It is the reference for the core supply. It must be connected to the system ground.
Note:
Each device in a system should have VDDF,VDDS, VDDQ and VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
14/23
M39P0R9080E0
Functional description
3
Functional description
The LPSDRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory and ES for the LPSDRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is a simultaneous read operations on the Flash memory and the LPSDRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram
VPPF VDDF A13-A24
EF WPF WF A0-A12 KF GF RPF LF DPDF VDDS VDDQ DQ0-DQ15 512 Mbit Flash Memory WAITF
BA0-BA1 ES WS KS KES CASS RASS UDQMS LDQMS 256 Mbit LPSDRAM
VSS
Ai12096
15/23
Functional description Table 2. Bus operations(1)
M39P0R9080E0
UDQMS/LDQMS X X X X X X
Operation
Bus Read Bus Write Flash memory Address Latch Output Disable Standby Reset
VIL VIL VIH VIL(4) VIH de-a(5) VIL VIH VIL VIL(4) VIH de-a(5) VIL X VIH VIL VIL VIH VIH VIH X X X X X X X X X X VIH de-a(5) VIH de-a(5) Hi-Z VIH de-a(5) Hi-Z VIL VIH de-a(5) Hi-Z Any SDRAM operation mode is allowed. The SDRAM must be disabled
Data Output Data Input Data Output or Hi-Z(6) Hi-Z Hi-Z Hi-Z Hi-Z VIL VIH VIL VIH VIH X X VIL V SCA BS V Data Output
Deep PowerVIH X Down Burst Read Burst Write Self Refresh Auto Refresh SDRAM Power-Down with Precharge
a(7) Hi-Z
The Flash memory must be disabled
VIL VIH VIL VIL VIH
VIL V SCA BS X Data Input X X X X X X - - X
VIL VIL VIL VIH VIH VIL VIL VIL VIL VIH VIH VIH VIL VIH VIH VIH VIH X X X VIH VIL
Deep PowerAny Flash memory operation mode VIL VIH VIH VIL VIH VIL Down is allowed Device VIH X X X VIH X Deselect No Operation VIL VIH VIH VIH VIH X
X X X X X
X X
1. X = Don't care, de-a = de-asserted, a = asserted, SCA = Start Column Address, BS = Bank Select, V = Valid. 2. The DPD signal polarity depends on the value of the ECR14 bit. 3. WAITF signal polarity is configured using the Set Configuration Register command. 4. LF can be tied to VIH if the valid address has been previously latched. 5. If ECR15 is set to '0', the device cannot enter the Deep Power-Down mode, even if DPDF is asserted. 6. Depends on GF. 7. ECR15 has to be set to `1' for the device to enter Deep Power-Down.
16/23
DQ15-DQ0 X X X
BA0-BA1
WAITF(3)
A9, A11
DPDF(2)
KESn-1
A0-A7
RASS
CASS
KESn
RPF
A10
WS
WF
GF
ES
EF
LF
M39P0R9080E0
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 3.
Symbol TA TBIAS TSTG VIO VDDF VDDS VDDQ VPPF IO tVPPH
Absolute maximum ratings
Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage LPSDRAM Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH -25 -25 -55 -0.5 -1.0 -0.5 -0.5 -1.0 Max 85 85 125 2.6 3.0 2.6 2.6 11.5 100 100 C C C V V V V V mA hours Unit
17/23
DC and AC parameters
M39P0R9080E0
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC measurement conditions
Parameter(1)(2) VDDF Supply Voltage VDDS Supply Voltage VDDQ Supply Voltage VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Impedance Output (Z0) Load Capacitance (CL) Output Circuit Protection Resistance (R) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
1. All voltages are referenced to VSS = 0V. 2. TA = 25C, f = 1MHz
Flash memory Min 1.7 - 1.7 8.5 -0.4 -25 Max 1.95 - 1.95 9.5 VDDQ+0.4 85 50 30 50 3 0 to VDDQ VDDQ/2
LPSDRAM Unit Min - 1.7 1.7 - - -25 Max - 1.95 1.95 - - 85 V V V V V C 30 pF 0.5 0.2 to 1.6 0.9 ns V V
Figure 4.
AC measurement I/O waveform
VDDQ VDDQ/2 0V
AI06161
18/23
M39P0R9080E0 Figure 5. AC measurement load circuit
VCCQ/2
DC and AC parameters
R DEVICE UNDER TEST
OUT Z0 CL
AI06162a
Table 5.
Symbol CIN COUT
Capacitance(1)
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min - - Max 12 15 Unit pF pF
1. Sampled only, not 100% tested.
Please refer to the M58PRxxxL and M65KA256AF datasheets for further DC and AC characteristics values and illustrations.
19/23
Package mechanical
M39P0R9080E0
6
Package mechanical
Figure 6. TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline
D D1 FD
e
E
E1
SE
ddd
BALL "A1"
FE A e b A1 A2
BGA-Z79
1. Drawing is not to scale.
Table 6.
Symbol
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data
millimeters Typ Min Max 1.20 0.20 0.80 0.35 9.00 6.40 0.10 11.00 8.80 0.80 1.30 1.10 0.40 - - 10.90 11.10 0.433 0.346 0.031 0.051 0.043 0.016 - - 0.429 0.30 8.90 0.40 9.10 0.031 0.014 0.354 0.252 0.004 0.437 0.012 0.350 0.016 0.358 0.008 Typ inches Min Max 0.047
A A1 A2 b D D1 ddd E E1 e FD FE SE
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M39P0R9080E0
Part numbering
7
Part numbering
Table 7.
Example:
Ordering information scheme
M39 P 0R 9 0 8 0E 0 ZAD E
Device Type M39 = Multi-Chip Package (Flash + LPSDRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VDDS = VDDQ = 1.7 to 1.95 V Flash 1 Density 9 = 512 Mbits Flash 2 Density 0 = No Die RAM 1 Density 8 = 256 Mbit RAM 0 Density 0 = No Die Parameter Blocks Location E = Even Block Flash Memory Configuration Product Version 0 = 90nm Flash technology, 96 ns speed; LPSDRAM Package ZAD = stacked TFBGA105 D stacked footprint. Option Blank = Standard Packing E = ECOPACK(R) Package, Standard packing F = ECOPACK(R) Package, Tape & Reel packing
Note:
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
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Revision history
M39P0R9080E0
8
Revision history
Table 8.
Date 15-Dec-2005
Document revision history
Revision 0.1 Initial release. Document status promoted from Target Specification to full Datasheet. Voltage ranges extended to 1.95V. Flash memory features updated to match the data in revision 2 of the M58PRxxxJ datasheet (random access time, programming time and VPPF modified). Table 2: Bus operations modified. VPPF max modified in Table 3: Absolute maximum ratings. Input Pulse voltages modified for SDRAM in Table 4: Operating and AC measurement conditions. Flash memory and SDRAM DC characteristics tables removed (see M58PRxxxJ and M65KA256AF datasheets for details). Applied Numonyx branding. Changes
12-Oct-2006
1
30-Nov-2007
2
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M39P0R9080E0
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved.
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